A programmable logic array (PLA) implements a desired logic or truth table by accepting a plurality of logical input signals and decoding them to provide a plurality of output signals. Typically, input signals are maintained in storage, for example, in a static latch, coupled to the input of the PLA until the particular combinatorial and/or sequential function implemented by the array is completed. The input signal decoding function is usually accomplished using two arrays of logic gates, typically referred to as the `AND` plane and the `OR` plane. The input signals are applied to the AND plane, which partially decodes them and applies the intermediate results as inputs to the OR plane. The terms AND and OR are representative of the Boolean algebra operations that are conventionally performed in the respective arrays. However, electrically both arrays are very similar, and comprise a series of signal line conductors whose voltage state represents the logical value of a given logic output term (OR plane), or intermediate result (AND plane).
The signal line conductors in both the AND and OR planes are precharged to a high voltage state in the case of a dynamic PLA. In the case of a static PLA, they are connected to a load device that tends to continuously pull them up to a high voltage state. In either case, logic transistors are connected in a desired parallel pattern between the signal lines and a reference voltage (e.g., ground). In order to perform a decoding operation, the input signals (or intermediate results) are applied to the control terminals of the logic transistors. If any of the logic transistors connected to a given signal line is thereby placed in the conductive state, the signal line is pulled down to the ground voltage state. Hence, electrically both the AND and OR planes perform a "NOR" operation.
The dynamic PLA design provides for low current consumption, since no dc current flows through the conductive logic transistors during a decode operation. However, clocks are required to switch between the precharge and decode operations for the AND and OR planes in a dynamic PLA. A first clock is applied to the AND plane, and a second clock (delayed relative to the first) is applied to the OR plane, so that the AND plane has sufficient time to complete its decode operation prior to performing the decode in the OR plane. The delay between the clocks must be sufficiently long to ensure that no erroneous discharge of a conductor occurs in the OR plane, since once discharged there is no further precharge signal available, and an erroneous output results. A disadvantage of using two clocks is that the circuit required for the clock signals does not readily fit in the area of either the AND or the OR plane, so that it must be placed externally thereto. This increases the area and complicates the layout of the integrated circuit, especially when computer aided design techniques utilizing geometrically regular blocks of circuitry are employed.
The present trend therefore is for the use of static arrays for both the AND and the OR planes. A static array beneficially eliminates the need for any clocks, since both planes are receptive to decoding input signals whenever they arrive. This approach also provides the smallest layout area. Unfortunately, in addition to drawing dc current whenever any of the logic transistors is in an "on" (i.e., conducting) state, a static PLA also consumes a measurable amount of power in the standby mode or idle state condition. Conventional static PLAs are known to consume considerably more dc power than a CMOS or dynamic PLA configuration.
In the portable computer industry the current practice is to enter a standby mode whenever the processor is idle or halted. Again, during standby mode the goal of the processing system is to consume minimal dc power, and thereby effect a minimal drain on the battery. The system is unable to power down completely, however, because the current state of the processor must be maintained when the user resumes operation. The standard power conserving technique employed for static PLAs is to terminate the internal clock to the various components of the static design simultaneous with initiation of the idle state condition. However, dc power (e.g., on the order of milliamps) continues to be consumed even with the internal clock stopped. This is due to the pull-up portion of the static PLA circuit. Given a sufficient period of time such a continuing dc power drain becomes significant for a battery based system.
Therefore, a need exists in the art for a logic macro and protocol which minimize (if not effectively eliminate) standby dc power drain through a logic array while in an idle state without subsequent loss of output state and without requiring that the outputs of said logic macro be stored prior to initiation of the idle state condition.